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A bus architecture for crosstalk elimination in high performance processor design

10 years 3 months ago
A bus architecture for crosstalk elimination in high performance processor design
In deep sub-micron technology, the crosstalk effect between adjacent wires has become an important issue, especially between long on-chip buses. This effect leads to the increase in delay, in power consumption, and in worst case, to incorrect result. In this paper, we propose a de-assembler/assembler structure to eliminate undesirable crosstalk effect on bus transmission. By taking advantage of the prefetch process where the instruction/data fetch rate is always higher than instruction/data commit rate in high performance processors, the proposed method would hardly reduce the performance. In addition, the required number of extra bus wires is only 7 as compared with 85 needed in [6] when the bus width is 128 bits. Categories and Subject Descriptors B.8.2 [Performance and Reliability]: Performance Analysis and Design Aids; C.1 [Processor Architecture]: Miscellaneous General Terms Performance, Design Keywords Crosstalk, Architecture, Instruction/Data Bus, High Performance
Wen-Wen Hsieh, Po-Yuan Chen, TingTing Hwang
Added 10 Jun 2010
Updated 10 Jun 2010
Type Conference
Year 2006
Where CODES
Authors Wen-Wen Hsieh, Po-Yuan Chen, TingTing Hwang
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