Bus mastering PCI express in an FPGA

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Bus mastering PCI express in an FPGA
This paper describes a bus mastering implementation of the PCI Express protocol using a Xilinx FPGA. While the theoretical peak performance of PCI Express is quite high, attaining that performance is a complex endeavor on top of an already complex protocol. The implementation is described and its performance is analyzed. Source code is offered for free download via the web. Categories and Subject Descriptors B.4.3 [Interconnections (Subsystems)] – Interfaces General Terms Design, Performance Keywords FPGA, PCI Express, PCIe, Bus Mastering, Design, Performance
Ray Bittner
Added 19 May 2010
Updated 19 May 2010
Type Conference
Year 2009
Where FPGA
Authors Ray Bittner
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