A Cache Architecture for Counting Bloom Filters

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A Cache Architecture for Counting Bloom Filters
— Within packet processing systems, lengthy memory accesses greatly reduce performance. To overcome this limitation, network processors utilize many different techniques, e.g., utilizing multi-level memory hierarchies, special hardware architectures, and hardware threading. In this paper, we introduce a multi-level memory hierarchy and a special hardware cache architecture for counting Bloom filters that is utilized by network processors and packet processing applications such as packet classification and distributed web caching systems. Based on the value of the counters in the counting Bloom filter, a multi-level cache architecture called the cache counting Bloom filter (CCBF) is presented and analyzed. The results show that the proposed cache architecture decreases the number of memory accesses by at
Mahmood Ahmadi, Stephan Wong
Added 03 Jun 2010
Updated 03 Jun 2010
Type Conference
Year 2007
Where ICON
Authors Mahmood Ahmadi, Stephan Wong
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