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2000
Springer

Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power

9 years 9 months ago
Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power
Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadvertently will lead to an exponential increase in leakage power dissipation. In this work we explore an architectural idea to reduce leakage power in data caches. Previous work has shown that cache frames are "dead" for a significant fraction of time [14]. We are exploiting this observation to turn off cache lines that are not likely to be accessed anymore. Our method is simple: if a cacheline is not accessed within a fixed interval (called decay interval) we turn off its supply voltage using a gated Vdd technique introduced previously [1]. We study the effect of cache-line decay on both power consumption and performance. We find that it is possible with cache-line decay to build larger caches that dissipate less leakage power than smaller caches while yielding equal or better performance (fewer misses). In addition, because our method can dynamically trade performance for leakage power it ca...
Stefanos Kaxiras, Zhigang Hu, Girija J. Narlikar,
Added 25 Aug 2010
Updated 25 Aug 2010
Type Conference
Year 2000
Where PACS
Authors Stefanos Kaxiras, Zhigang Hu, Girija J. Narlikar, Rae McLellan
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