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GLVLSI
2009
IEEE

Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip

11 years 8 months ago
Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip
In the context of nanoscale networks-on-chip (NoCs), each link implementation solution is not just a specific synthesis optimization technique with local performance and power implications, but gives rise to a well-differentiated point in the architecture design space. This in an effect of the tight interaction existing between architecture and physical design layers in nanoscale technologies. This work assesses several NoC link inference techniques (buffering options, link pipelining) by means of commercial backend synthesis tools, taking the system-level perspective. In fact, performance speed-ups and power overhead are not evaluated for the links in isolation but for the network topology as a whole, thus showing their sensitivity to the link inference strategy. k-ary nmesh topologies are considered for the sake of analysis, in that they provide a range of topologies with increasing total wirelength.
Daniele Ludovici, Georgi Nedeltchev Gaydadjiev, Da
Added 21 May 2010
Updated 21 May 2010
Type Conference
Year 2009
Where GLVLSI
Authors Daniele Ludovici, Georgi Nedeltchev Gaydadjiev, Davide Bertozzi, Luca Benini
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