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GI
2009
Springer

Challenges of Electronic CAD in the Nano Scale Era

11 years 4 months ago
Challenges of Electronic CAD in the Nano Scale Era
: Future nano scale devices will expose different characteristics than todays silicon devices. While the exponential growth of non recurring expenses (NRE, mostly due to mask sets) can be anticipated even for new technologies, problems such as the dramatically increased defect density require new approaches to build functional devices at reasonable prices. Improved CAD algorithms can help to solve these problems, or in some cases, they can be seen as enabling technology to broaden the use of paradigms such as reconfigurable computing. In this work we discuss in which stages of design, manufacturing, and deployment new CAD algorithms are required. 1 How to make Productive use of Billions of Logic Gates Following the road of Moore’s law, the number of transistors on a chip doubles every 24 months. After being valid for more than 40 years, the end of Moore’s law has been forecast many times now. Yet, technological advances have keep the progress intact. While the technological foreca...
Christian Hochberger, Andreas Koch
Added 24 Jul 2010
Updated 24 Jul 2010
Type Conference
Year 2009
Where GI
Authors Christian Hochberger, Andreas Koch
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