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2009
IEEE

Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors

9 years 8 months ago
Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors
Translation Lookaside Buffers (TLBs) are a staple in modern computer systems and have a significant impact on overall system performance. Numerous prior studies have addressed TLB designs to lower access times and miss rates; these, however, have been targeted towards uniprocessor architectures. As the computer industry embraces chip multiprocessor (CMP) architectures, it is important to study the TLB behavior of emerging parallel workloads. This work presents the first full-system characterization of the TLB behavior of emerging parallel applications on real-system CMPs. Using the PARSEC benchmarks, representative of emerging RMS workloads, we show that TLB misses can hinder system performance significantly. We also evaluate TLB miss stream patterns and show that multiple threads of a parallel execution experience a large number of redundant and predictable misses. For our evaluated benchmarks, 30% to 95% of the total misses fall under this category. Our results point to the need ...
Abhishek Bhattacharjee, Margaret Martonosi
Added 24 May 2010
Updated 24 May 2010
Type Conference
Year 2009
Where IEEEPACT
Authors Abhishek Bhattacharjee, Margaret Martonosi
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