Charge sharing fault analysis and testing for CMOS domino logic circuits

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Because domino logic design offers smaller area and faster delay than conventional CMOS design, it is very popular in the high-performance processor design. However, domino logic suffers from several design problems and one of the most notable ones is the chargesharing problem. In this paper, we describe a method to measure the sensitivity of the charge-sharing problem for each domino gate. In addition, our algorithm also generates test vectors to detect the worst case of chargesharing fault.

Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Sh

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Added	30 Jul 2010
Updated	30 Jul 2010
Type	Conference
Year	2000
Where	ATS
Authors	Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang

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Charge sharing fault analysis and testing for CMOS domino logic circuits

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