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ISPD
1998
ACM

CHDStd - application support for reusable hierarchical interconnect timing views

13 years 7 months ago
CHDStd - application support for reusable hierarchical interconnect timing views
This paper describes an important new facility for timing-driven design applications within the new CHDStd standard for a SEMATECH design system for large complex chips. We first review EDA requirements for CHDStd hierarchy for large complex leading edge chips and current EDA problems in accurately and efficiently handling complex interconnect. We then describe our approach for fully-reusable hierarchical interconnect timing views in support of timing driven design for 0.25u technologies and below. The result is a method which builds on SEMATECH's new controlled error parasitic timing calculation capability for deep submicron, providing means for compactly storing and reusing accurate hierarchical timing views for 28M to 100M transistor chip designs.
S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher,
Added 05 Aug 2010
Updated 05 Aug 2010
Type Conference
Year 1998
Where ISPD
Authors S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, D. Cottrell, D. Mallis, S. DasGupta, J. Morrell, Amrich Chokhavtia
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