Checking Delay-Insensitivity: 104 Gates and Beyond

Wire and gate delays are accounted to have equal, or nearly equal, effect on circuit behavior in modern design techniques. This paper introduces a new approach to verify circuits whose behavior is independent of component delays (delay-insensitive). It shows that for a particular way of implementing a delay-insensitive circuit, through a Null Convention Logic methodology, the complexity of the verification task might be significantly reduced. This method is implemented using Satisfiability (SAT)-solvers and is successfully tested on realistic design examples having tens of thousands of gates.

• Type: Conference
• Year: 2002
• Where: ASYNC
• Authors: Alex Kondratyev, Oriol Roig, Lawrence Neukom, Karl Fant, Alexander Taubin
• Keywords: ASYNC 2002, Gate Delays, Hardware, Modern Design Techniques, Null Convention Logic