The Chimaera reconfigurable functional unit

By strictly separating reconfigurable logic from their host processor, current custom computing systems suffer from a significant communication bottleneck. In this paper we describe Chimaera, a system that overcomes this bottleneck by integrating reconfigurable logic into the host processor itself. With direct access to the host processor’s register file, the system enables the creation of multi-operand instruction and a speculative execution model key to high performance, general-purpose reconfigurable computing. It also supports multi-output functions, and utilizes partial run-time reconfiguration to reduce reconfiguration time. Combined, this system can provide speedups of a factor of two or more for general-purpose computing, and speedups of 160 or more are possible for hand-mapped applications.

• Type: Conference
• Year: 1997
• Where: FCCM
• Authors: Scott Hauck, Thomas W. Fry, Matthew M. Hosler, Jeffrey P. Kao
• Keywords: FCCM 1997, General-purpose Reconfigurable Computing, Host Processor, Reconfigurable Logic, VLSI