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ISQED
2007
IEEE

On-Chip Inductance in X Architecture Enabled Design

9 years 7 months ago
On-Chip Inductance in X Architecture Enabled Design
The inductance effects become significant for sub-100nm process designs due to increasing interconnect lengths, lower interconnect resistance values and fast signal transition times. The accurate modeling of inductance behavior is thus essential for high speed VLSI designs. Recently X Architecture has been introduced to reduce overall IC interconnect length by using diagonal wirings pervasively, resulting in smaller die sizes and higher performance. Although the resistance and capacitance of diagonal wires and their modeling are well understood, the characterization and modeling studies of diagonal wire inductance remain scarce. In this paper, we study the inductance effects of diagonal wiring, specifically inductance with return loop through diagonal (X Architecture) and Manhattan power grids. Both self and mutual inductance of Manhattan and diagonal wirings in the presence of various power grids are obtained using both FastHenry simulations and on-chip measurements. Results show tha...
Santosh Shah, Arani Sinha, Li Song, Narain D. Aror
Added 04 Jun 2010
Updated 04 Jun 2010
Type Conference
Year 2007
Where ISQED
Authors Santosh Shah, Arani Sinha, Li Song, Narain D. Arora
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