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DAC
2010
ACM

Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms

9 years 4 months ago
Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms
We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system design is the widening gap between the memory demand generated by the processor cores and the limited off-chip memory bandwidth and memory service speed. This severely restricts the number of cores that can be integrated into a multi-core system and the parallelism that can be actually achieved and efficiently exploited for not only memory demanding applications, but also for workloads consisting of many tasks utilizing a large number of cores and thus exceeding the available off-chip bandwidth. Last level shared cache partitioning has been shown to be a promising technique to enhance cache utilization and reduce missrates. While most cache partitioning techniques focus on cache miss rates, our work takes a different approach in which tasks’ memory bandwidth requirements are taken into account when identi...
Chenjie Yu, Peter Petrov
Added 15 Aug 2010
Updated 15 Aug 2010
Type Conference
Year 2010
Where DAC
Authors Chenjie Yu, Peter Petrov
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