On-Chip Time Measurement Architecture with Femtosecond Timing Resolution

This paper presents a new on-chip time measurement architecture which is based on the Timeto-Digital Conversion (TDC) method that is capable of achieving a timing resolution of tens of femtoseconds without the use of external automatic test equipment (ATE). This is the highest temporal resolution that has been reported to-date and is achieved by the use of the homodyne technique. The proposed architecture has been designed using a 0.12

• Type: Conference
• Year: 2006
• Where: ETS
• Authors: Matthew Collins, Bashir M. Al-Hashimi
• Keywords: ETS 2006, Hardware, On-chip Time Measurement, Time Measurement Architecture, Timing Resolution