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ISQED
2009
IEEE

On-chip transistor characterization arrays with digital interfaces for variability characterization

10 years 11 months ago
On-chip transistor characterization arrays with digital interfaces for variability characterization
An on-chip test-and-measurement system with digital interfaces that can perform device-level characterization of large-dense arrays of transistors is demonstrated in 90- and 65-nm technologies. The collected variability data from the 90-nm run is used to create a statistical device model based on BSIM4.3 to capture random variability. Principal component analysis (PCA) is used to extract a reduced set of purely random variables from a set of correlated BSIM4.3 parameters. Different layout-dependent systematic effects, related to poly- and active-flares, STI-stress, and lithography limitations, are examined in both technologies. These layout-dependent effects are mapped to systematic shifts in BSIM4.3 and BSIM4.4 model parameters in 90- and 65-nm, respectively. Keywords CMOS, variability, modeling, statistical, PCA, measurement, on-chip, characterization, arrays, transistor
Simeon Realov, William McLaughlin, Kenneth L. Shep
Added 19 May 2010
Updated 19 May 2010
Type Conference
Year 2009
Where ISQED
Authors Simeon Realov, William McLaughlin, Kenneth L. Shepard
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