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ISCAS
2007
IEEE

Clock Gating and Negative Edge Triggering for Energy Recovery Clock

9 years 5 months ago
Clock Gating and Negative Edge Triggering for Energy Recovery Clock
Energy recovery clocking has been demonstrated as an effective method for reducing the clock power. In this method the conventional square wave clock signal is replaced by a sinusoidal clock generated by a resonant circuit. Such a modification in clock signal prevents application of existing clock gating solutions. In this paper, we propose a clock gating solution for energy recovery clocking by gating the flip-flops. Applying our clock gating to the energy recovery clocked flip-flops reduces their power by 1000X in the idle mode with negligible power and delay overhead in the active mode. Applying the proposed clock gating technique to a system of 1000 flip-flops with idle mode probability and data switching activity of 50%, reduces the total power by 47%. We also propose a negative edge triggering solution for the energy recovery clocked flip-flops.
Vishwanadh Tirumalashetty, Hamid Mahmoodi
Added 04 Jun 2010
Updated 04 Jun 2010
Type Conference
Year 2007
Where ISCAS
Authors Vishwanadh Tirumalashetty, Hamid Mahmoodi
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