Clock power reduction for virtex-5 FPGAs

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Clock power reduction for virtex-5 FPGAs
Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presented. The approaches are unique in that they leverage specific architectural aspects of Virtex-5 to achieve reductions in dynamic power consumed by the clock network. The first approach comprises a placement-based technique to reduce interconnect resource usage on the clock network, thereby reducing capacitance and power (up to 12%). The second approach borrows the “clock gating” notion from the ASIC domain and applies it to FPGAs. Clock enable signals on flip-flops are selectively migrated to use the dedicated clock enable available on the FPGA’s built-in clock network, leading to reduced toggling on the clock interconnect and lower power (up to 28%). Power reductions are achieved without any performance penalty, on average. Categories and Subject Descriptors B.7 [Integrated Circuits]: Design Aids G...
Qiang Wang, Subodh Gupta, Jason Helge Anderson
Added 19 May 2010
Updated 19 May 2010
Type Conference
Year 2009
Where FPGA
Authors Qiang Wang, Subodh Gupta, Jason Helge Anderson
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