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ISCAS
2007
IEEE

CMOS SOCs at 100 GHz: System Architectures, Device Characterization, and IC Design Examples

9 years 5 months ago
CMOS SOCs at 100 GHz: System Architectures, Device Characterization, and IC Design Examples
—This paper investigates the suitability of 90nm and 65nm GP and LP CMOS technology for SOC applications in the 60GHz to 100GHz range. Examples of system architectures and transceiver building blocks are provided which emphasize the need for aggressively scaled GP CMOS and low-VT transistors if CMOS is to compete with SiGe BiCMOS above 60 GHz. This requirement is in conflict with the 2005-ITRS proposal to use LP CMOS for RF applications.
S. P. Voinigescu, S. T. Nicolson, M. Khanpour, K.
Added 04 Jun 2010
Updated 04 Jun 2010
Type Conference
Year 2007
Where ISCAS
Authors S. P. Voinigescu, S. T. Nicolson, M. Khanpour, K. K. W. Tang, K. H. K. Yau, N. Seyedfathi, A. Timonov, A. Nachman, G. Eleftheriades, P. Schvan, M. T. Yang
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