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2002
IEEE

Coarse-Grain Pipelining on Multiple FPGA Architectures

9 years 11 months ago
Coarse-Grain Pipelining on Multiple FPGA Architectures
Reconfigurable systems, and in particular, FPGA-based custom computing machines, offer a unique opportunity to define application-specific architectures. These architectures offer performance advantages for application domains such as image processing, where the use of customized pipelines exploits the inherent coarse-grain parallelism. In this paper we describe a set of program analyses and an implementation that map a sequential and un-annotated C program into a pipelined implementation running on a set of FPGAs, each with multiple external memories. Based on well-known parallel computing analysis techniques, our algorithms perform unrolling for operator parallelization, reuse and data layout for memory parallelization and precise communication analysis. We extend these techniques for FPGA-based systems to automatically partition the application data and computation into custom pipeline stages, taking into account the available FPGA and interconnect resources. We illustrate the anal...
Heidi E. Ziegler, Byoungro So, Mary W. Hall, Pedro
Added 14 Jul 2010
Updated 14 Jul 2010
Type Conference
Year 2002
Where FCCM
Authors Heidi E. Ziegler, Byoungro So, Mary W. Hall, Pedro C. Diniz
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