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IMSCCS
2006
IEEE

CoarseZ Buffer Bandwidth Model in 3D Rendering Pipeline

10 years 10 months ago
CoarseZ Buffer Bandwidth Model in 3D Rendering Pipeline
Depth traffic occupies a major portion of 3D graphics memory bandwidth. In order to reduce depth reading, we propose employing a low-resolution depth buffer, namely CoarseZ buffer, for tile-level depth culling before perpixel test. The maximum depth of a tile is stored in the corresponding entry of CoarseZ buffer. Simulation results show that a small CoarseZ buffer can achieve remarkably high culling rate and significantly reduce z-reading bandwidth. We build a model that quantifies the influence of the CoarseZ design parameters on its efficiency and bandwidth. Test results of industrial benchmarks show that CoarseZ with tile size of 4 and bit depth of 16 can be a best selection to reduce memory bandwidth.
Ke Yang, Ke Gao, Jiaoying Shi, Xiaohong Jiang, Hua
Added 11 Jun 2010
Updated 11 Jun 2010
Type Conference
Year 2006
Where IMSCCS
Authors Ke Yang, Ke Gao, Jiaoying Shi, Xiaohong Jiang, Hua Xiong
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