Combitgen: A new approach for creating partial bitstreams in Virtex-II Pro

Today's FPGAs (Field Programmable Gate Arrays) are widely used, but not to their full potential. In Virtex series FPGAs from Xilinx a special feature, the dynamic and partial reconfiguration is available. This feature enables a designer to create a system on chip with a static area and a reconfigurable part that can be exchanged during run-time while the remaining static portion is still operational. In this paper we present a new technique that combines the advantages of already existing partial dynamic reconfiguration flows for Xilinx Virtex FPGAs. The method reduces unnecessary frames in bitstreams without increasing their quantity. In our simple example design we could achieve an improvement of the reconfiguration times up to 8 percent compared to a common matchable reconfiguration method. Our approach also surpasses all Xilinx generated bitstreams in terms of reconfiguration times.

• Type: Conference
• Year: 2006
• Where: ARCS
• Authors: Christopher Claus, Florian Helmut Müller, Walter Stechele
• Keywords: ARCS 2006, Partial Reconfiguration, Reconfiguration Times, Software Engineering, Virtex Series Fpgas