Communication Scheduling

The high arithmetic rates of media processing applications require architectures with tens to hundreds of functional units, multiple register files, and explicit interconnect between functional units and register files. Communication scheduling enables scheduling to these emerging architectures, including those that use shared buses and register file ports. Scheduling to these shared interconnect architectures is difficult because it requires simultaneously allocating functional units to operations and buses and register file ports to the communications between operations. Prior VLIW scheduling algorithms are limited to clustered register file architectures with no shared buses or register file ports. Communication scheduling extends the range of target architectures by making each communication explicit and decomposing it into three components: a write stub, zero or more copy operations, and a read stub. Communication scheduling allows media processing kernels to achieve 98% of the p...

• Type: Conference
• Year: 2000
• Where: ASPLOS
• Authors: Peter R. Mattson, William J. Dally, Scott Rixner, Ujval J. Kapasi, John D. Owens
• Keywords: ASPLOS 2000, File Ports, Programming Languages, Register File, Register File Architecture