Compact, multilayer layout for butterfly fat-tree

9 years 11 months ago
Compact, multilayer layout for butterfly fat-tree
Modern VLSI processing supports a two-dimensional surface for active devices along with multiple stacked layers of interconnect. With the advent of planarization, the number of layers can be large (6 or 7 in modern designs) and more layers are feasible if the cost is justified. Using a multilayer-wiring VLSI area model, we show how a butterfly fat-tree (or fat-pyramid) with N processors can be laid out in (N) active device area using (log(N)) wiring layers. This result may have practical value in laying out efficient, singlechip multiprocessors and FPGAs. It may also provide a theoretical basis for the rate of layer scaling empirically seen in VLSI designs. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and Design Styles--VLSI; C.2.1 [Computer-Communication Networks]: Network Architecture
André DeHon
Added 25 Aug 2010
Updated 25 Aug 2010
Type Conference
Year 2000
Where SPAA
Authors André DeHon
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