Compaction Schemes with Minimum Test Application Time

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Compaction Schemes with Minimum Test Application Time
Testing embedded cores in a System-on-a-chip necessitates the use of a Test Access Mechanism, which provides for transportation of the test data between the chip and the core I/Os. To relax the requirements on the test access mechanism at the core output side, we outline a space and time compaction scheme which minimizes test application time and required test bandwidth at the same time. To implement a computationally feasible algorithm that searches for such an optimal compaction circuitry, we formulate the constraints, which avoid aliasing, on a mathematical basis. The experimental results illustrate that not only is performance optimized but furthermore the associated area overhead is low as well.
Ozgur Sinanoglu, Alex Orailoglu
Added 23 Aug 2010
Updated 23 Aug 2010
Type Conference
Year 2001
Where ATS
Authors Ozgur Sinanoglu, Alex Orailoglu
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