A Compile-Time Partitioning Strategy for Non-Rectangular Loop Nests

This paper presents a compile-time scheme for partitioning non-rectangular loop nests which consist of inner loops whose bounds depend on the index of the outermost, parallel loop. The minimisation of load imbalance, on the basis of symbolic cost estimates, is considered the main objective; however, options which may increase other sources of overhead are avoided. Experimental results on a virtual shared memory computer are also presented.

• Type: Conference
• Year: 1997
• Where: IPPS
• Authors: Rizos Sakellariou
• Keywords: Compile-time Scheme, Distributed And Parallel Computing, IPPS 1997, Non-rectangular Loop Nests, Symbolic Cost Estimates