A compiler-directed data prefetching scheme for chip multiprocessors

Data prefetching has been widely used in the past as a technique for hiding memory access latencies. However, data prefetching in multi-threaded applications running on chip multiprocessors (CMPs) can be problematic when multiple cores compete for a shared on-chip cache (L2 or L3). In this paper, we (i) quantify the impact of conventional data prefetching on shared caches in CMPs. The experimental data collected using multi-threaded applications indicates that, while data prefetching improves performance in small number of cores, its benefits reduce significantly as the number of cores is increased, that is, it is not scalable; (ii) identify harmful prefetches as one of the main contributors for degraded performance with a large number of cores; and (iii) propose and evaluate a compiler-directed data prefetching scheme for shared on-chip cache based CMPs. The proposed scheme first identifies program phases using static compiler analysis, and then divides the threads into groups within...

• Type: Conference
• Year: 2009
• Where: PPOPP
• Authors: Dhruva Chakrabarti, Mahmut T. Kandemir, Mustafa Karaköy, Seung Woo Son
• Keywords: Data Prefetching Scheme, Multiple Cores, Parallel Computing, PPOPP 2009, Shared On-chip Cache