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2010

Complexity dichotomy on degree-constrained VLSI layouts with unit-length edges

8 years 7 months ago
Complexity dichotomy on degree-constrained VLSI layouts with unit-length edges
Deciding whether an arbitrary graph admits a VLSI layout with unit-length edges is NP-complete [1], even when restricted to binary trees [7]. However, for certain graphs, the problem is polynomial or even trivial. A natural step, outstanding thus far, was to provide a broader classification of graphs that make for polynomial or NP-complete instances. We provide such a classification based on the set of vertex degrees in the input graphs, yielding a comprehensive dichotomy on the complexity of the problem, with and without the restriction to trees.
Vinícius G. P. de Sá, Celina M. Herr
Added 10 Dec 2010
Updated 10 Dec 2010
Type Journal
Year 2010
Where ENDM
Authors Vinícius G. P. de Sá, Celina M. Herrera de Figueiredo, Guilherme Dias da Fonseca, Raphael Machado
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