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2002
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Concurrent flip-flop and repeater insertion for high performance integrated circuits

9 years 9 months ago
Concurrent flip-flop and repeater insertion for high performance integrated circuits
For many years, CMOS process scaling has allowed a steady increase in the operating frequency and integration density of integrated circuits. Only recently, however, have we reached a point where it takes several clock cycles for global signals to traverse a complex digital system such as a modern microprocessor. Thus, interconnect latency must be taken into account in current and future design tools at the architectural as well as synthesis level. To this purpose, this work proposes a new latencyaware technique for the performance-driven concurrent insertion of flipflops and repeaters in VLSI circuits. Overwhelming evidence showing an exponential increase in the number of pipelined interconnects with process scaling, for high-performance microprocessors as well as highend ASICs, is also presented. This increase indicates a radical change in current design methodologies to cope with this new emerging problem.
Pasquale Cocchini
Added 16 Mar 2010
Updated 16 Mar 2010
Type Conference
Year 2002
Where ICCAD
Authors Pasquale Cocchini
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