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6

ICCAD
1999
IEEE

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Concurrent logic restructuring and placement for timing closure

13 years 8 months ago

Concurrent logic restructuring and placement for timing closure

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: In this paper, an algorithm for simultaneous logic restructuring and placement is presented. This algorithm first constructs a set of super-cells along the critical paths and then generates the set of non-inferior re-mapping solutions for each supercell. The best mapping and placement solutions for all super-cells are obtained by solving a generalized geometric programming (GGP) problem. The process of identifying and optimizing the critical paths is iterated until timing closure is achieved. Experimental results on a set of MCNC benchmarks demonstrate the effectiveness of our algorithm.

Jinan Lou, Wei Chen, Massoud Pedram

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Critical Paths | Hardware | ICCAD 1999 | Non-inferior Re-mapping Solutions | Simultaneous Logic Restructuring |

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Added	03 Aug 2010
Updated	03 Aug 2010
Type	Conference
Year	1999
Where	ICCAD
Authors	Jinan Lou, Wei Chen, Massoud Pedram

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