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1996
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Conservative Circuit Simulation on Shared-Memory Multiprocessors

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Conservative Circuit Simulation on Shared-Memory Multiprocessors
We investigate conservative parallel discrete event simulations for logical circuits on shared-memory multiprocessors. For a first estimation of the possible speedup, we extend the critical path analysis technique by partitioning strategies. To incorporate overhead due to the management of data structures, we use a simulation on an ideal parallel machine (PRAM). This simulation can be directly executed on the SB-PRAM prototype, yielding both an implementation and a basis for data structure optimizations. One of the major tools to achieve these is the SB-PRAM's hardware support for parallel prefix operations. Our reimplementation of the PTHOR program on the SB-PRAM yields substantially higher speedups than before.
Jörg Keller, Thomas Rauber, Bernd Rederlechne
Added 08 Aug 2010
Updated 08 Aug 2010
Type Conference
Year 1996
Where PADS
Authors Jörg Keller, Thomas Rauber, Bernd Rederlechner
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