Constructing Virtual Architectures on a Tiled Processor

As the amount of available silicon resources on one chip increases, we have seen the advent of ever increasing parallel resources integrated on-chip. Many architectures use these resources as individually controllable, parallel processing elements. While such architectures excel at parallel applications, they seldom support legacy single-threaded applications. In this work, we propose using parallel resources to facilitate execution of legacy codes with acceptable performance on parallel architectures containing a drastically different instruction set through the use of an all software parallel dynamic binary translation engine. This engine spatially implements different portions of a superscalar processor across distinct parallel elements thus exploiting the pipeline parallelism inherent in a superscalar. This virtual microarchitecture facilitates changing the allocation of silicon resources between different superscalar units in software which is not possible when special purpose ph...

• Type: Conference
• Year: 2006
• Where: CGO
• Authors: David Wentzlaff, Anant Agarwal
• Keywords: Architectures, CGO 2006, Parallel Architectures, Parallel Resources, Software Engineering