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DATE
2010
IEEE

Construction of dual mode components for reconfiguration aware high-level synthesis

13 years 8 months ago
Construction of dual mode components for reconfiguration aware high-level synthesis
High-level synthesis has recently started to gain industrial acceptance, due to the improved quality of results and the multi-objective optimizations offered. One optimization area lately addressed is reconfigurable computing, where parts of a DFG are merged and mapped into coarse grained reconfigurable components. This paper presents an alternative approach, the construction of dual mode components which are exchanged with regular components in the resulting RTL architecture. The dual mode components are constructed by exhaustive search for dual mode functional primitives inside the datapath of complicated RTL components. Such components, like multipliers and dividers, that would remain idle in certain control steps, are able to work full-time in two different modes, without any reconfiguration overhead applied to the critical path of the application. The results obtained with different DSP benchmarks show an average performance gain of 15%, without any practical datapath area increas...
George Economakos, Sotirios Xydis, Ioannis Koutras
Added 02 Aug 2010
Updated 02 Aug 2010
Type Conference
Year 2010
Where DATE
Authors George Economakos, Sotirios Xydis, Ioannis Koutras, Dimitrios Soudris
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