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DSD
2007
IEEE

On the Construction of Small Fully Testable Circuits with Low Depth

13 years 10 months ago
On the Construction of Small Fully Testable Circuits with Low Depth
During synthesis of circuits for Boolean functions area, delay and testability are optimization goals that often contradict each other. Multi-level circuits are often quite small while circuits with low depth are often larger regarding the area requirements. A different optimization goal is good testability which can usually only be achieved by additional hardware overhead. In this paper we propose a synthesis technique that allows to trade-off between area and delay. Moreover, the resulting circuits are 100% testable under the stuck-at fault model. The proposed approach relies on the combination of 100% testable circuits derived from binary decision diagrams and 2-SPP networks. Full testability under the stuck-at fault model is proven and experimental results show the trade-off between area and depth.
Görschwin Fey, Anna Bernasconi, Valentina Cir
Added 02 Jun 2010
Updated 02 Jun 2010
Type Conference
Year 2007
Where DSD
Authors Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler
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