Creating a power-aware structured ASIC

In an attempt to enable the cost-effective production of lowand mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architectures. These architectures represent a departure from traditional standard-cell-based ASIC designs in favor of techniques which present more physical and structural regularity. This paper presents circuits which provide powerperformance flexibility in this regular, structured ASIC environment. These circuits, which employ gate sizing and voltage scaling for energy efficiency, enable delay-constrained power optimization to be performed for structured ASIC designs. Categories and Subject Descriptors: B.6.1 [Logic Design]: Design styles—Logic Arrays; B.6.3 [Logic Design]: Design aids—Optimization General Terms: Performance, Design

• Type: Conference
• Year: 2004
• Where: ISLPED
• Authors: R. Reed Taylor, Herman Schmit
• Keywords: ASIC Designs, ISLPED 2004, Structured Asic, Structured Asic Architectures