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ASAP
2007
IEEE

Customizing Reconfigurable On-Chip Crossbar Scheduler

10 years 3 months ago
Customizing Reconfigurable On-Chip Crossbar Scheduler
We present a design of a customized crossbar scheduler for on-chip networks. The proposed scheduler arbitrates on-demand interconnects, where physical topologies are identical to logical topologies for given applications. Considering conventional fully parallel and sequential schedulers as reference designs, a comparative performance analysis is conducted. The hardware scheduler module is implemented with parameterized arbiter arrays. Experiments with practical applications show that the crossbar network with our custom scheduler realizes on-demand traffic patterns, occupies on average 52% less area, and maintains higher performance, compared to the crossbar network with a fully parallel scheduler. Additionally, our custom scheduler performs significantly better than the sequential scheduler with moderate area overheads for smallsized tokens communicated over large networks.
Jae Young Hur, Todor Stefanov, Stephan Wong, Stama
Added 12 Aug 2010
Updated 12 Aug 2010
Type Conference
Year 2007
Where ASAP
Authors Jae Young Hur, Todor Stefanov, Stephan Wong, Stamatis Vassiliadis
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