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Decimal Floating-Point Division Using Newton-Raphson Iteration

8 years 7 months ago
Decimal Floating-Point Division Using Newton-Raphson Iteration
Decreasing feature sizes allow additional functionality to be added to future microprocessors to improve the performance of important application domains. As a result of rapid growth in financial, commercial, and Internet-based applications, hardware support for decimal floating-point arithmetic is now being considered by various computer manufacturers and specifications for decimal floating-point arithmetic have been added to the draft revision of the IEEE-754 Standard for Floating-Point Arithmetic (IEEE-754R). This paper presents an efficient arithmetic algorithm and hardware design for decimal floating-point division. The design uses an optimized piecewise linear approximation, a modified NewtonRaphson iteration, a specialized rounding technique, and a simplified combined decimal incrementer/decrementer. Synthesis results show that a 64-bit (16-digit) implementation of the decimal divider, which is compliant with IEEE-754R, has an estimated critical path delay of 0.69 ns when imple...
Liang-Kai Wang, Michael J. Schulte
Added 20 Aug 2010
Updated 20 Aug 2010
Type Conference
Year 2004
Where ASAP
Authors Liang-Kai Wang, Michael J. Schulte
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