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GLVLSI
2008
IEEE

Delay driven AIG restructuring using slack budget management

10 years 13 hour ago
Delay driven AIG restructuring using slack budget management
Timing optimizations during logic synthesis has become a necessary step to achieve timing closure in VLSI designs. This often involves “shortening” all paths found in the circuit at a cost of increasing the circuit area. In contrast, we present a synthesis approach which leverages slack budgeting to effectively minimize the critical path length without increasing the area of the design. Our results confirm that this is an effective method to control area while optimizing for delay. When compared to an area driven logic synthesis flow, we achieve a 32% reduction in logic depth and an 11% reduction in circuit delay when placed by VPR [1]; and when compared against a depth controlled logic synthesis flow without slack budgeting, we achieve an 8% reduction in logic depth and a 3% reduction in circuit delay when placed by VPR [1]. In both cases, the area penalty is negligible. Categories and Subject Descriptors B.6.3 [Hardware]: Logic Design - Design Aids General Terms Algorithms, E...
Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown
Added 29 May 2010
Updated 29 May 2010
Type Conference
Year 2008
Where GLVLSI
Authors Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown
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