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11

PATMOS
2004
Springer

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138views Modeling and Simulation» more PATMOS 2004»

Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic

13 years 9 months ago

Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic

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The main result is the development, and delay comparison based on Logical Eﬀort, of a number of high speed circuits for common arithmetic and related operations using threshold logic. The designs include 8 to 64-input AND, 4-bit carry generate, and the carry-out of a (7,3) parallel (population) counter. The circuits are designed using both domino gates and the recently proposed CMOS Charge Recycling Threshold Logic (CRTL). It is shown that compared to domino, the

Peter Celinski, Derek Abbott, Sorin Cotofana

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4-bit Carry Generate | Delay Comparison | PATMOS 2004 | Threshold Logic |

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Added	02 Jul 2010
Updated	02 Jul 2010
Type	Conference
Year	2004
Where	PATMOS
Authors	Peter Celinski, Derek Abbott, Sorin Cotofana

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