Delay-Insensitive Carry-Lookahead Adders

Integer addition is one of the most important operations in digital computer systems because the performance of processors is significantly influenced by the speed of their adders. This paper proposes a delay-insensitive, carrylookahead adder in which the logic complexity is a linear function of n, the number of inputs, and the average computation time is proportional to the logarithm of the logarithm of n. We also show an economic implementation of this adder in CMOS technology.

• Type: Conference
• Year: 1997
• Where: VLSID
• Authors: Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald, Wen-Chung Cho
• Keywords: Average Computation Time, Carrylookahead Adder, Integer Addition, VLSI, VLSID 1997