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2010

Design and Analysis of On-Chip Networks for Large-Scale Cache Systems

9 years 5 months ago
Design and Analysis of On-Chip Networks for Large-Scale Cache Systems
—Switched networks have been adopted in on-chip communication for their scalability and efficient resource sharing. However, using a general network for a specific domain may result in unnecessary high cost and low performance when the interconnects are not optimized for the domain. Designing an optimal network for the specific domain is challenging because in-depth knowledge of interconnects and the application domain is required. Recently proposed Nonuniform Cache Architectures (NUCAs) use wormhole-routed 2D mesh networks in L2 caches. We observe that in NUCAs, network resources are underutilized with the considerable area cost (41 percent of cache) and the network delay is significantly large (63 percent of cache access time). Motivated by our observations, we investigate both router architecture and network topology for communication behaviors in large-scale cache systems. We present Fast-LRU replacement, where cache replacement overlaps with data request delivery. Next, we propo...
Yuho Jin, Eun Jung Kim, Ki Hwan Yum
Added 30 Jan 2011
Updated 30 Jan 2011
Type Journal
Year 2010
Where TC
Authors Yuho Jin, Eun Jung Kim, Ki Hwan Yum
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