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ICCD
1999
IEEE

Design and Evaluation of a Selective Compressed Memory System

9 years 8 months ago
Design and Evaluation of a Selective Compressed Memory System
This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compressed form. However, decompression time causes a critical effect on the memory access time and variable-sized compressed blocks tend to increase the design complexity of the compressed cache architecture. This paper suggests several techniques to reduce the decompression overhead and to manage the compressed blocks efficiently, which include selective compression, fixed space allocation for the compressed blocks, parallel decompression, the use of a decompression buffer, and so on. Moreover, a simple compressed cache architecture based on the above techniques and its management method are proposed. The results from trace-driven simulation show that this approach can provide around 35% decrease in the on-chip cache miss ratio as well as a 53% decrease in the data traffic over the conventional memory systems. Also,...
Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim
Added 03 Aug 2010
Updated 03 Aug 2010
Type Conference
Year 1999
Where ICCD
Authors Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim
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