Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs

—This paper proposes a novel technique to exploit the high bandwidth offered by through silicon vias (TSVs). In the proposed approach, synchronous parallel 3D links are replaced by serialized links to save silicon area and increase yield. Detailed analysis conducted in 90 nm CMOS technology shows that the proposed 2-Gb/s/pin quasi-serial link requires approximately five times less area than its parallel bus equivalent at same data rate for a TSV diameter of 20 μm. Keywords-3D integration; through silicon via; serial link; parallel link; 3D NoC

• Type: Journal
• Year: 2010
• Where: VLSI
• Authors: Fengda Sun, Alessandro Cevrero, Panagiotis Athanasopoulos, Yusuf Leblebici
• Keywords: Nm Cmos Technology, Silicon, Silicon Vias, Software Engineering, VLSI 2010