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2004
Springer

Design and Implementation of a CFAR Processor for Target Detection

9 years 11 months ago
Design and Implementation of a CFAR Processor for Target Detection
Real-time performance of adaptive digital signal processing algorithms is required in many applications but it often means a high computational load for many conventional processors. In this paper, we present a configurable hardware architecture for adaptive processing of noisy signals for target detection based on Constant False Alarm Rate (CFAR) algorithms. The architecture has been designed to deal with parallel/pipeline processing and to be configured for three versions of CFAR algorithms, the Cell-Average, the Max and the Min CFAR. The architecture has been implemented on a Field Programmable Gate Array (FPGA) with a good performance improvement over software implementations. Results are presented and discussed.
Cesar Torres-Huitzil, René Cumplido-Parra,
Added 01 Jul 2010
Updated 01 Jul 2010
Type Conference
Year 2004
Where FPL
Authors Cesar Torres-Huitzil, René Cumplido-Parra, Santos López-Estrada
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