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2005
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Design and Optimization of Low-Voltage Low-Power Quasi-Floating Gate Digital Circuits

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Design and Optimization of Low-Voltage Low-Power Quasi-Floating Gate Digital Circuits
This paper explores the design and optimization of Quasi-Floating Gate MOS techniques to lowvoltage/low-power digital circuitry. The simulated power consumption of standard CMOS gates is compared to that of QFGMOS implementations in a 0.18µm process for different supply voltages and device sizes. A 0.4V VDD full-adder biased for propagation delay similar to that of 0.8V CMOS is
Kenneth A. Townsend, James W. Haslett, Krzysztof I
Added 25 Jun 2010
Updated 25 Jun 2010
Type Conference
Year 2005
Where IWSOC
Authors Kenneth A. Townsend, James W. Haslett, Krzysztof Iniewski
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