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VTS
2003
IEEE

Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs

13 years 9 months ago
Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs
Multi-level TAM optimization is necessary for modular testing of hierarchical SOCs that contain older-generation SOCs as embedded cores. We present two hierarchical TAM optimization flows that exploit recent advances in TAM design for flattened SOC hierarchies. Unlike prior methods that assume flat test hierarchies, the proposed methods are directly applicable to real-world design transfer models between the core vendor and the SOC integrator. Experimental results are presented for four ITC’02 SOC Test Benchmarks.
Vikram Iyengar, Krishnendu Chakrabarty, Mark D. Kr
Added 05 Jul 2010
Updated 05 Jul 2010
Type Conference
Year 2003
Where VTS
Authors Vikram Iyengar, Krishnendu Chakrabarty, Mark D. Krasniewski, Gopind N. Kumar
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