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11

ICCAD
2001
IEEE

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The Design and Optimization of SOC Test Solutions

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The Design and Optimization of SOC Test Solutions

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1 We propose an integrated technique for extensive optimization of the ﬁnal test solution for System-on-Chip using Simulated Annealing. The produced results from the technique are a minimized test schedule fulﬁlling test conﬂicts under test power constraints and an optimized design of the test access mechanism. We have implemented the proposed algorithm and performed experiments with several benchmarks and industrial designs to show the usefulness and efﬁciency of our technique.

Erik Larsson, Zebo Peng, Gunnar Carlsson

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Hardware | ICCAD 2001 | Minimized Test Schedule | Test Access Mechanism | Test Power Constraints |

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Added	17 Mar 2010
Updated	17 Mar 2010
Type	Conference
Year	2001
Where	ICCAD
Authors	Erik Larsson, Zebo Peng, Gunnar Carlsson

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