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INFOCOM
1999
IEEE

Design and Performance of a Web Server Accelerator

9 years 20 days ago
Design and Performance of a Web Server Accelerator
We describe the design, implementation and performance of a Web server accelerator which runs on an embedded operating system and improves Web server performance by caching data. The accelerator resides in front of one or more Web servers. Our accelerator can serve up to 5000 pages/second from its cache on a 200 MHz PowerPC 604. This throughput is an order of magnitude higher than that which would be achieved by a high-performance Web server runningon similar hardware under a conventional operating system such as Unix or NT. The superior performance of our system results in part from its highly optimized communications stack. In order to maximize hit rates and maintain updated caches, our accelerator provides an API which allows application programs to explicitly add, delete, and update cached data. The API allows our accelerator to cache dynamic as well as static data. We analyze the SPECweb96 benchmark, and show that the accelerator can provide high hit ratios and excellent performa...
Eric Levy-Abegnoli, Arun Iyengar, Junehwa Song, Da
Added 03 Aug 2010
Updated 03 Aug 2010
Type Conference
Year 1999
Where INFOCOM
Authors Eric Levy-Abegnoli, Arun Iyengar, Junehwa Song, Daniel M. Dias
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