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2006
IEEE

Design Challenges for High Performance Nano-Technology

10 years 2 months ago
Design Challenges for High Performance Nano-Technology
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design challenges that are experienced in microprocessor designs. It will capture the design issues in the areas of high level architectural modeling, design for manufacturability (DFM), layout synthesis, standard cell design, and performance verification. It will describe the requirements to meet power, timing, physical dimension and process portability goals with nano-technology. It will also address the pre and post silicon verification difficulties that have a direct impact on taking the product to market. This tutorial covers the following main topics in detail: • Expectation from the VLSI product (Moore’s law, Higher performance, higher clock speed, smaller die, lower dynamic and static power, higher reliability) • High level Modeling Challenges that includes power modeling, performance analysis, DFT and ...
Goutam Debnath, Paul J. Thadikaran
Added 12 Jun 2010
Updated 12 Jun 2010
Type Conference
Year 2006
Where VLSID
Authors Goutam Debnath, Paul J. Thadikaran
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