Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits

Metallic Carbon Nanotubes (CNTs) create source-drain shorts in Carbon Nanotube Field Effect Transistors (CNFETs), causing excessive leakage, degraded noise margin and delay variation. There is no known CNT growth technique that guarantees 0% metallic CNTs. Therefore, metallic CNT removal techniques are necessary. Unfortunately, such removal techniques alone are imperfect and insufficient. This paper demonstrates the necessity for co-optimization of processing techniques for metallic CNT removal together with CNFETbased circuit design. We present a probabilistic CNFET circuit model which forms the basis for such co-optimization, and use the model to derive design and processing guidelines that enable design of CNFET-based digital circuits with practical constraints on leakage, noise margin and delay variations. These guidelines are essential for designing robust metalliccarbon-nanotube-tolerant digital circuits.

• Type: Conference
• Year: 2008
• Where: DATE
• Authors: Jie Zhang, Nishant Patil, Subhasish Mitra
• Keywords: DATE 2008, Hardware, Metallic Cnt, Metallic Cnt Removal, Removal Techniques