Sciweavers

Share
GLVLSI
2003
IEEE

Design issues in low-voltage high-speed current-mode logic buffers

9 years 4 months ago
Design issues in low-voltage high-speed current-mode logic buffers
- A current-mode logic (CML) buffer is based on a simple differential circuit. This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a chain of tapered CML buffers is proposed. The circuit design issues in regard to the CML buffer are compared with those in a conventional CMOS inverter. It is shown, both through the experiments and by using efficient analytical models, why CML buffers are better than CMOS inverters in high-speed low-voltage applications.
Payam Heydari
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where GLVLSI
Authors Payam Heydari
Comments (0)
books